In the fabrication of semiconductor integrated circuits (ICs), active device regions arc formed in semiconductor substrates, isolated from adjacent devices with an isolating material. Electrical paths connect such active devices, using thin-film structures, such as metal lines/patterned metal layers. Such structures make contact with active devices through openings, or contact holes, in the isolating material. One primary concern in forming such interconnects is the maintenance of a low level of resistivity throughout an IC in order to ensure devices perform properly. As ICs are scaled down in size, so are the devices which make up the ICs. Increases in resistance are associated with increasing circuit density and adversely affect device performance, slowing them down and increasing power consumption. Thus, ways to decrease the overall resistance of ICs are crucial to continued successful device performance.
In many applications, the metal lines/patterned metal layers are formed on a different level than the active devices, separated by an insulating layer, such as, for example, silicon dioxide or borophosphosilicate glass (BPSG). Furthermore, there may be more than one level of metal lines/patterned metal layers, connected by conductive interconnects formed in vias defined in an insulating layer between adjacent metal lines/patterned metal layers. Commonly used metal lines/patterned metal layers include aluminum, to which copper may be added to form an alloy. Interconnects are also formed between individual devices and the metal lines/patterned metal layers. A typical interconnect to an active device region is formed in a contact hole defined in an insulating layer over the active device region. The contact hole is filled with one or more metals, such as, for example, aluminum or tungsten.
In lowering resistivity of an IC, it is important to remove all foreign residue from interfaces in the IC. As multiple layers are formed in ICs, individual layers may need to be cleaned before the next layer is formed or before surface modification is done. Numerous preclean procedures exist for use prior to semiconductor surface modification in batch furnaces, including wet chemical cleans, hydrogen bakes, phosphoric acid, and hydrofluoric acid (HF) vapor cleans. Many cleaning compositions undesirably contain strong, i.e., not dilute, organic solvents, which typically are disposed of using special hazardous waste disposal techniques.
Preclean procedures are important to both reduce native oxide and remove other contaminants, such as, for example, residual organic and metallic impurities. Residual photoresist and other organic materials used in processing steps, such as, for example, etches, are often hard to remove from surfaces during IC fabrication. In particular, such residual materials are hard to remove from metal surfaces and surfaces adjacent to metal layers due to the metallization of such organic residue on the surfaces, particularly as a result of intermixing of materials during etch steps. Thus, metal layers and vias have been hard to effectively clean in the past after completion of patterning etches and via etches through insulating layers thereon. Further, conventional cleaning compositions used are typically hazardous and require special handling and disposal procedures.
Therefore, for the reasons as described above, there is a need for effective cleaning compositions and methods of cleaning surfaces during fabrication of ICs. For example, a composition and method for cleaning metal surfaces during fabrication is needed to remove metallized organic residue from surfaces during IC fabrication in order to lower the resistivity of resulting ICs. Further, it is desirable that the cleaning compositions utilized can be disposed of safely and easily.